SN54LS10 डाटा शीट PDF( Datasheet )

SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D

SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDLS035A – DECEMBER 1983 – REVISED APRIL 2003 PRODUCTION DATA information is current as of publication date. Products

SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW tran

SN54107, SN54LS107A, SN74107, SN74LS107A DUAL J-K FLIP-FLOPS WITH CLEAR SDLS036 – DECEMBER 1983 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to speci

SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and f

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device JM38510/30109BEA Status Package Type Package Pins Package (1) Drawing Qty ACTIVE CDIP J 16 1 Eco Plan (2) TBD J