डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
MK2049-45 | 3.3V Communications Clock PLL MK2049-45
3.3V Communications Clock PLL
Description
The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pu |
Integrated Circuit Systems |
|
MK2049-45 | CLOCK PLL 3.3 VOLT COMMUNICATIONS CLOCK PLL
DATASHEET
MK2049-45
Description
The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO bas |
Renesas |
|
MK2049-45 | CLOCK PLL 3.3 VOLT COMMUNICATIONS CLOCK PLL
DATASHEET
MK2049-45A
Description
The MK2049-45A is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO b |
Renesas |
www.DataSheet.in | 2017 | संपर्क |