M48Z2M1 डाटा शीट PDF( Datasheet )

M48Z2M1 M48Z2M1Y 16 Mb (2Mb x 8) ZEROPOWER® SRAM INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERIES CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENC

M48Z2M1Y M48Z2M1V 5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER® SRAM Not recommended for new design Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and batteries ■ Conventional

M48Z2M1Y M48Z2M1V 5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER® SRAM Not recommended for new design Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and batteries ■ Conventional