डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
CY7C265 | 8K x 8 Registered PROM 65
CY7C265
8K x 8 Registered PROM
Features
• CMOS for optimum speed/power • High speed (Commercial) — 15 ns address set-up — 12 ns clock to output • Low power — 660 mW (Commercial) • On-chip edg |
Cypress Semiconductor |
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CY7C2644KV18 | 144-Mbit QDR II+ SRAM Two-Word Burst Architecture | Cypress Semiconductor |
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CY7C266 | 8Kx8 Power-Switched and Reprogrammable PROM | Cypress Semiconductor |
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CY7C263 | 8K x 8 Power-Switched and Reprogrammable PROM | Cypress Semiconductor |
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CY7C261 | 8K x 8 Power-Switched and Reprogrammable PROM | Cypress Semiconductor |
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CY7C2663KV18 | 144-Mbit QDR II+ SRAM Four-Word Burst Architecture | Cypress Semiconductor |
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CY7C265 | 8K x 8 Registered PROM | Cypress Semiconductor |
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CY7C2665KV18 | 144-Mbit QDR II+ SRAM Four-Word Burst Architecture | Cypress Semiconductor |
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CY7C2642KV18 | 144-Mbit QDR II+ SRAM Two-Word Burst Architecture | Cypress Semiconductor |
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CY7C264 | 8K x 8 Power-Switched and Reprogrammable PROM | Cypress Semiconductor |
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CY7C2670KV18 | 144-Mbit DDR II+ SRAM Two-Word Burst Architecture | Cypress Semiconductor |
www.DataSheet.in | 2017 | संपर्क |