CY7C147 डाटा शीट PDF( Datasheet )

7c147: 12/4/89 Revision: Thursday, November 11, 1993 www.DataSheet4U.com Features D D D D D D D Automatic powerĆdown when deseĆ lected CMOS for optimum speed/power High speed Capable of withstanding gre

CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features ■ ■ Functional Description The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are

CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features

CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit (2M × 36/4M × 18/1M × 72) Pipelined SRAM with NoBL™ Architecture 72-Mbit (2M × 36/4M × 18/1M × 72) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-

www.DataSheet4U.com CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT™ • Support

CY7C1471BV25 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency™ (NoBL™) architecture elim

CY7C1471BV33 CY7C1473BV33 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No bus latency™ (NoB