डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
CY7C130 | 1K x 8 Dual-Port Static RAM CY7C130, CY7C130A CY7C131, CY7C131A
CY7C140, CY7C141
1K x 8 Dual-Port Static RAM
Features
■ True dual-ported memory cells, which allow simultaneous reads of the same memory location
■ 1K x 8 organization
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Cypress Semiconductor |
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CY7C1302CV25 | 9-Mbit Burst of Two Pipelined SRAMs www.DataSheet4U.com
PREMILINARY
CY7C1302CV25
9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture
Features
• Separate independent Read and Write data ports — Supports concurrent transactions • |
Cypress Semiconductor |
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CY7C1302DV25 | 9-Mbit Burst of Two Pipelined SRAMs www.DataSheet4U.com
PREMILINARY
CY7C1302DV25
9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture
Features
• Separate independent Read and Write data ports — Supports concurrent transactions • |
Cypress Semiconductor |
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CY7C1303BV18 | 18-Mbit Burst of 2 Pipelined SRAM CY7C1303BV18 CY7C1306BV18
18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture
Features
Functional Description
• Separate independent Read and Write data ports — Supports concurrent transactions
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Cypress Semiconductor |
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CY7C1303BV25 | 18-Mbit Burst of Two-Pipelined SRAM CY7C1303BV25
18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture
18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture
Features
■ Separate independent read and write data ports ❐ Supports con |
Cypress Semiconductor |
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CY7C1304DV25 | 9-Mbit Burst of 4 Pipelined SRAM PRELIMINARY
CY7C1304DV25
9-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture
Features
• Separate independent Read and Write data ports — Supports concurrent transactions
• 167-MHz Clock for high |
Cypress Semiconductor |
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CY7C1305BV18 | 18-Mbit Burst of 4 Pipelined SRAM CY7C1305BV18 CY7C1307BV18
18-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture
Features
Functional Description
• Separate independent Read and Write data ports — Supports concurrent transactions
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Cypress Semiconductor |
www.DataSheet.in | 2017 | संपर्क |