| No. | Partie # | Fabricant | Description | Fiche Technique |
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IDT |
6-output 1.8V PCIe Gen1-2-3 ZDB/FOB • 6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF additive cycle-to-cycle jitter <5ps • DIF output-to-output skew <60ps • DIF additive phase jitter is <100fs rms for PCIe Gen3 • DIF additive phase jitter <300fs rms for SGMII Bloc |
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Renesas |
6-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer • Six 1 –200 MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF additive cycle-to-cycle jitter < 5ps • DIF output-to-output skew < 60ps • PCIe Gen5 CC additive phase jitter < 40fs RMS • 12kHz –20MHz additive phase jitter = 156fs RMS at 156.25MH |
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