74LS10 डाटा शीट PDF( Datasheet )
डेटा पत्रक ( Datasheet PDF ) |
| भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
| 74LS10 | TRIPLE 3-INPUT NAND GATE SN54/74LS10 TRIPLE 3-INPUT NAND GATE
TRIPLE 3-INPUT NAND GATE
VCC 14 13 12 11 10 9 8
LOW POWER SCHOTTKY
1
2
3
4
5
6
7 GND
14 1
J SUFFIX CERAMIC CASE 632-08
14 1
N SUFFIX PLASTIC CASE 646-06
14 1
D |
 ON Semiconductor |
|
| 74LS10 | Triple 3-Input NAND Gate DM74LS10 Triple 3-Input NAND Gate
August 1986 Revised March 2000
DM74LS10 Triple 3-Input NAND Gate
General Description
This device contains three independent gates each of which performs the logic NAND functi |
 Fairchild Semiconductor |
|
| 74LS107 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
June 1989
DM54LS107A DM74LS107A Dual Negative-EdgeTriggered Master-Slave J-K Flip-Flops with |
 ETC |
|
| 74LS109 | Dual J-K Flip-Flop www.DataSheet4U.com
www.DataSheet4U.com
www.DataSheet4U.com
www.DataSheet4U.com
|
 Agere Systems |
|
| 74LS109A | LOW POWER SCHOTTKY www.DataSheet4U.com
SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop
The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent |
ON Semiconductor |
|
| 74LS109A | Dual J-K Positive-Edge-Triggered Flip-Flops www.ti.com
PACKAGE OPTION ADDENDUM
4-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Eco Plan
(1)
Drawing
Qty
(2)
JM38510/30109BEA JM38510/30109BFA JM38510/3010 |
 etcTI |
शेयर लिंक :
[1]
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