| No. | Partie # | Fabricant | Description | Fiche Technique |
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NXP |
Dual D-type flip-flop • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V • Balanced propagation delays • Inputs accepts voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input |
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Samsung Electronics |
Dual D-Type Positive-Edge-Triggered Flip-Flops |
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nexperia |
Dual D-type flip-flop and benefits • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Input levels: • For 74AHC74: CMOS level • For 74AHCT74: TTL level • ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V |
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nexperia |
Dual D-type flip-flop and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher |
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nexperia |
Dual D-type flip-flop and benefits • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Input levels: • For 74AHC74: CMOS level • For 74AHCT74: TTL level • ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V |
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nexperia |
Dual D-type flip-flop and benefits • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Input levels: • For 74AHC74: CMOS level • For 74AHCT74: TTL level • ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V |
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nexperia |
Dual D-type flip-flop and benefits • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Input levels: • For 74AHC74: CMOS level • For 74AHCT74: TTL level • ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V |
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Texas Instruments |
Dual Positive-Edge-Triggered D-Type Flip-Flops the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION{ TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 125°C SOIC − |
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Texas Instruments |
Dual Positive-Edge-Triggered D-Type Flip-Flops justifying use of this component beyond specified performance and environmental limits. D OR PW PACKAGE (TOP VIEW) 1CLR 1 1D 2 1CLK 3 1PRE 4 1Q 5 1Q 6 GND 7 14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q description/ordering information The SN74 |
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Texas Instruments |
Dual Positive-Edge-Triggered D-Type Flip-Flops • Operating range of 4.5 V to 5.5 V • Low power consumption, 10-µA maximum ICC • ±8-mA output drive at 5 V • Inputs are TTL-voltage compatible • Latch-up performance exceeds 250 mA per JESD 17 2 Applications • Convert a momentary switch to a toggle s |
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