डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
SN74LS10 | TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE
SN54/74LS10
VCC 14 13 12 11 10
9
8
TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY
1234567 GND
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambie |
Motorola |
|
SN74LS10 | TRIPLE 3-INPUT POSITIVE-NAND GATES SN5410, SN54LS10, SN54S10, SN7410, SN74LS10, SN74S10 TRIPLE 3-INPUT POSITIVE-NAND GATES
SDLS035A – DECEMBER 1983 – REVISED APRIL 2003
PRODUCTION DATA information is current as of publication date. Products |
etcTI |
|
SN74LS10 | TRIPLE 3-INPUT NAND GATE SN74LS10
TRIPLE 3-INPUT NAND GATE
VCC 14 13
12
11 10
9
8
1234567 GND
Symbol VCC
Supply Voltage
Parameter
TA Operating Ambient Temperature Range
IOH Output Current — High IOL Output Current — Low
|
ON Semiconductor |
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SN74LS107A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the |
Motorola |
|
SN74LS107A | DUAL J-K FLIP-FLOPS SN54107, SN54LS107A,
SN74107, SN74LS107A
DUAL J-K FLIP-FLOPS WITH CLEAR
SDLS036 – DECEMBER 1983 – REVISED MARCH 1988
PRODUCTION DATA information is current as of publication date. Products conform to speci |
etcTI |
|
SN74LS109 | LOW POWER SCHOTTKY SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop
The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall tim |
ON Semiconductor |
|
SN74LS109A | Dual JK Positive Edge-Triggered Flip-Flop SN74LS109A
Dual JK Positive Edge−Triggered Flip−Flop
The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall |
ON Semiconductor |
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