PLL102-15 डाटा शीट PDF( Datasheet )
डेटा पत्रक ( Datasheet PDF ) |
| भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
| PLL102-15 | Low Skew Output Buffer PLL102-15
Low Skew Output Buffer
FEATURES
Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation). � |
 PhaseLink Corporation |
|
| PLL102-15 | Low Skew Output Buffer | PhaseLink Corporation |
|
| PLL102-108 | Programmable DDR Zero Delay Clock Driver | PhaseLink Corporation |
|
| PLL102-10 | Low Skew Output Buffer | PhaseLink Corporation |
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| PLL102-109 | Programmable DDR Zero Delay Clock Driver | PhaseLink Corporation |
शेयर लिंक :
[1]
www.DataSheet.in | 2017 | संपर्क |