डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
PLL102-109 | Programmable DDR Zero Delay Clock Driver Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
FEATURES
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of si |
PhaseLink Corporation |
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PLL102-10 | Low Skew Output Buffer | PhaseLink Corporation |
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PLL102-108 | Programmable DDR Zero Delay Clock Driver | PhaseLink Corporation |
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PLL102-109 | Programmable DDR Zero Delay Clock Driver | PhaseLink Corporation |
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