PLL102-10 डाटा शीट PDF( Datasheet )

PLL102-10 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs. • Zero input - output delay. •

PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of ten differential

Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of si