LTC695 डाटा शीट PDF( Datasheet )

Features n Guaranteed Reset Assertion at VCC = 1V n 1.5mA Maximum Supply Current n Fast (35ns Max) Onboard Gating of RAM Chip Enable Signals n SO-8 and S16 Packaging n 4.65V Precision Voltage Monitor n P

LTC694-3.3/LTC695-3.3 3.3V Microprocessor Supervisory Circuits FEATURES n Guaranteed Reset Assertion at VCC = 1V n Pin Compatible with LTC694/LTC695 for 3.3V Systems n 200μA Typical Supply Current n Fast (30n

Features LTC6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution Description n Low Phase Noise and Jitter n Additive Jitter: 18fsRMS (12kHz to 20MHz) n Additive Jitter: 85fsRMS (10Hz to Nyqu

LTC6952 Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B/JESD204C Support FEATURES nn JESD204B/C, Subclass 1 SYSREF Signal Generation nn Low Noise Integer-N PLL nn Additive Output Jitter < 6fsRMS (Inte

Preliminary Technical Data FEATURES nn LTC6955: 11 Output Buffer nn LTC6955-1: 10 Buffered Outputs and One ÷2 Output nn Additive Output Jitter ~45fs RMS (ADC SNR Method) nn Additive Output Jitter < 5fs RMS (I

Features n Low Phase Noise Buffer/Driver n Optimized Conversion of Sine Wave Signals to Logic Levels n Three Logic Output Types Available – LVPECL – LVDS – CMOS n Additive Jitter 45fsRMS (LTC6957

Features n Low Phase Noise Buffer/Driver n Optimized Conversion of Sine Wave Signals to Logic Levels n Three Logic Output Types Available – LVPECL – LVDS – CMOS n Additive Jitter 45fsRMS (LTC6957