IS61QDPB44M18A fiche technique

No.	Partie #	Fabricant	Description
1	IS61QDPB44M18A1	ISSI	72Mb QUADP (Burst 4) SYNCHRONOUS SRAM  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  D
2	IS61QDPB44M18A2	ISSI	72Mb QUADP (Burst 4) SYNCHRONOUS SRAM  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  D
3	IS61QDPB44M18A	ISSI	72Mb QUADP (Burst 4) SYNCHRONOUS SRAM  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  D