IS61DDB44M18 डाटा शीट PDF( Datasheet )

I7D7D2DMR-bII (2M x 36 & 4M x (Burst o. f 4) CIO 18) Synchronous SRAMs A MAY 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common I/O read and wr

IS61DDB44M18A IS61DDB42M36A 4Mx18, 2Mx36 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM JANUARY 2015 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid w