IS61DDB24M18 डाटा शीट PDF( Datasheet )

72 Mb (2M x 36 & 4M x 18) . DDR-II (Burst of 2) CIO Synchronous SRAMs November 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/outpu

IS61DDB24M18A IS61DDB22M36A 4Mx18, 2Mx36 72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM AUGUST 2014 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid wi

IS61DDB24M18C IS61DDB22M36C 4Mx18, 2Mx36 72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration available.  Common I/O read and write ports.  Max. 400 MHz clock