डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
HD74HC11 | Triple 3-input AND Gates HD74HC11
Triple 3-input AND Gates
Features
• • • • • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input C |
Hitachi Semiconductor |
|
HD74HC11 | Triple 3-input AND Gates HD74HC11
Triple 3-input AND Gates
Features
• High Speed Operation: tpd = 9 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Cur |
Renesas |
|
HD74HC112 | Dual J-K Flip-Flops HD74HC112
Dual J-K Flip-Flops (with Preset and Clear)
Description
Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and c |
Hitachi Semiconductor |
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HD74HC112 | Dual J-K Flip-Flops HD74HC112
Dual J-K Flip-Flops (with Preset and Clear)
REJ03D0562-0200 (Previous ADE-205-435)
Rev.2.00 Oct 11, 2005
Description
Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q ou |
Renesas |
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HD74HC113 | Dual J-K Flip-Flops HD74HC113
Dual J-K Flip-Flops (with Preset)
Description
This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, |
Hitachi Semiconductor |
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HD74HC113 | Dual J-K Flip-Flops HD74HC113
Dual J-K Flip-Flops (with Preset)
REJ03D0563-0200 (Previous ADE-205-436)
Rev.2.00 Oct 11, 2005
Description
This flip-flop is edge sensitive to the clock input and change state on the negative going t |
Renesas |
|
HD74HC114 | Dual J-K Flip-Flops HD74HC114
Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)
Description
This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each f |
Hitachi Semiconductor |
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