| No. | Partie # | Fabricant | Description | Fiche Technique |
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Excelliance MOS |
Single N-Channel Logic Level Enhancement Mode Field Effect Transistor mbient3 RθJA 1Pulse width limited by maximum junction temperature. 2Duty cycle < 1％ 362.5°C / W when mounted on a 1 in2 pad of 2 oz copper. 4Guarantee by Engineering test TYPICAL 2020/7/20 A.1 EMD04N10E LIMITS ±20 171 108 16 12 543 100 500.0 |
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