CD74HCT10 डाटा शीट PDF( Datasheet )

CDx4HCT10 Triple 3-Input NAND Gates CD74HCT10, CD54HCT10 SCHS404 – JUNE 2020 1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 µA

Data sheet acquired from Harris Semiconductor SCHS139D March 1998 - Revised October 2003 CD54HC107, CD74HC107, CD74HCT107 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC107 , CD74 HCT10

Data sheet acquired from Harris Semiconductor SCHS140E March 1998 - Revised October 2003 CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74

CDx4HCT10 Triple 3-Input NAND Gates CD74HCT10, CD54HCT10 SCHS404 – JUNE 2020 1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 µA

CDx4HCT10 Triple 3-Input NAND Gates CD74HCT10, CD54HCT10 SCHS404 – JUNE 2020 1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 µA