AX125 डाटा शीट PDF( Datasheet )

v2.7 Axcelerator Family FPGAs u e ™ Leading-Edge Performance • • • • • • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capa

AX1250ES 2A Sink/Source Bus Termination Regulator  GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (

AX1250S 1.5A Sink/Source Bus Termination Regulator  GENERAL DESCRIPTION AX1250S is a linear regulator designed as a cost-effective solution for active termination of DDR SDRAM. The converting voltage range