AD9142 डाटा शीट PDF( Datasheet )

Data Sheet FEATURES Very small inherent latency variation: <2 DAC clock cycles Proprietary low spurious and distortion design 6-carrier GSM ACLR = 79 dBc at 200 MHz IF SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF

Data Sheet Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter AD9142A FEATURES Supports input data rate up to 575 MHz Very small inherent latency variation: <2 DAC clock cycles Proprietary low spurio