A54SXxx डाटा शीट PDF( Datasheet )

v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es • 320 MHz Internal Performance • 3.7 ns Clock-to-Out (Pin-to-Pin) • 0.1 ns Input Set-Up • 0.25 ns Clock Skew Sp e ci f ic at i

v5.1 SX-A Family FPGAs Leading-Edge Performance • • 250 MHz System Performance 350 MHz Internal Performance • • • • • • • • • • ™ Specifications • • • • 12,000 to 108,000 Av