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74LS73 डाटा शीट PDF( Datasheet )


डेटा पत्रक ( Datasheet PDF )

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74LS73   Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with C
Fairchild Semiconductor
Fairchild Semiconductor
PDF
74LS73   Dual J-K Flip-Flops

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value
Hitachi Semiconductor
Hitachi Semiconductor
PDF
74LS73   DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are e
Motorola
Motorola
PDF
74LS73A   Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with C
Fairchild Semiconductor
Fairchild Semiconductor
PDF
74LS73A   Dual J-K Flip-Flops

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value
Hitachi Semiconductor
Hitachi Semiconductor
PDF



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