74LS48 डाटा शीट PDF( Datasheet )

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value

SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates and one driver are connected in pairs

DM74LS48 BCD to 7-Segment Decoder January 1992 DM74LS48 BCD to 7-Segment Decoder General Description The ’LS48 translates four lines of BCD (8421) input data into the 7-segment numeral code and provides sev