74LS26 डाटा शीट PDF( Datasheet )

54LS26/74LS26 LSTTL 型 2 输入四与非门(高压， OC) 典型参数： tpd=16ns Pd=2.0mW/每门 逻辑符号： 线路图（1/4） 逻辑式： 逻辑表： 外引线排列图： 推荐工作条件 74�

7426 54LS/74LS26 QUAD 2-INPUT NAND BUFFER (W ith O p en-C o llecto r Outputs) 26 CONNECTION DIAGRAM PINOUT A ORDERING CODE: See Section 9 PKGS PIN OUT COMMERCIAL GRADE Vcc = +5.0 V ±5%, Ta = 0°C to +70°

DM74LS26 Quad 2-Input NAND Gate with High Voltage Open-Collector Outputs August 1986 Revised March 2000 DM74LS26 Quad 2-Input NAND Gate with High Voltage Open-Collector Outputs General Description This devic

QUAD 2-INPUT NAND BUFFER • ESD > 3500 Volts SN54/74LS26 VCC 14 13 12 11 10 9 8 * * * * 1 2 3 4 5 6 7 GND * OPEN COLLECTOR OUTPUTS GUARANTEED OPERATING RANGES Symbol Parameter VCC Supply

SN54/74LS260 DUAL 5-INPUT NOR GATE VCC 14 13 12 11 10 9 8 DUAL 5-INPUT NOR GATE LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND J SUFFIX CERAMIC CASE 632-08 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFF

DM74LS266 Quad 2-Input Exclusive-NOR Gate March 1989 Revised March 2000 DM74LS266 Quad 2-Input Exclusive-NOR Gate with Open-Collector Outputs General Description This device contains four independent gates ea

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value