डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
74LS112A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are |
Motorola |
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74LS112A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000
DM74LS112A
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Fl |
Fairchild Semiconductor |
www.DataSheet.in | 2017 | संपर्क |