डेटा पत्रक ( Datasheet PDF ) |
भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
74LS11 | Triple 3-Input AND Gate DM74LS11 Triple 3-Input AND Gate
August 1986 Revised March 2000
DM74LS11 Triple 3-Input AND Gate
General Description
This device contains three independent gates each of which performs the logic AND function. |
Fairchild Semiconductor |
|
74LS112 | Dual J-K Negative-edge-triggered Flip-Flops 19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
Hitachi Code JEDEC EIAJ Weight (reference value)
+ 0.1 |
Hitachi Semiconductor |
|
74LS112A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are |
Motorola |
|
74LS112A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000
DM74LS112A
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Fl |
Fairchild Semiconductor |
|
74LS114A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that |
Motorola |
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