74F114 डाटा शीट PDF( Datasheet )
डेटा पत्रक ( Datasheet PDF ) |
| भाग संख्या | विवरण | मैन्युफैक्चरर्स | |
| 74F114 | Dual JK Negative Edge-Triggered Flip-Flop 74F114 Dual JK Negative Edge-Triggered Flip-Flop
April 1988 Revised August 1999
74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
General Description
The 74F114 contains two high- |
 Fairchild Semiconductor |
|
| 74F112 | Dual J-K negative edge-triggered flip-flop |  NXP |
|
| 74F112 | Dual JK Negative Edge-Triggered Flip-Flop | Fairchild Semiconductor |
|
| 74F11 | Triple 3-input NAND gate | NXP |
|
| 74F11 | Triple 3-Input AND Gate | Fairchild Semiconductor |
|
| 74F11 | Triple 3-Input AND Gate |  National Semiconductor |
|
| 74F113 | Dual JK Negative Edge-Triggered Flip-Flop | Fairchild Semiconductor |
|
| 74F113 | Dual J-K negative edge-triggered flip-flops | NXP |
|
| 74F114 | Dual JK Negative Edge-Triggered Flip-Flop | Fairchild Semiconductor |
|
| 74F112 | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP |  etcTI |
|
| 74F11 | Triple 3-Input AND Gate | etcTI |
शेयर लिंक :
[1]
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