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Motorola |
Quad D Flip-Flop |
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ON Semiconductor |
Quad D Flip-Flop Q3 D3 D2 Q2 Q2 CP 16 15 14 13 12 11 10 9 12345678 MR Q0 Q0 D0 D1 Q1 Q1 GND Figure 1. Pinout: 16−Lead Packages (Top View) PIN ASSIGNMENT PIN FUNCTION D0 − D3 CP Data Inputs Clock Pulse Input MR Master Reset Input Q0 − Q3 Q0 − Q3 Outputs Outp |
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AVG Semiconductor |
Quad D Flip-Flop |
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Renesas |
Quad D-Type Flip-Flop • Edge-Triggered D-Type Inputs • Buffered Positive Edge-Triggered Clock • Asynchronous Common Reset • True and Complement Output • Outputs Source/Sink 24 mA • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abb |
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Motorola Inc |
QUAD D FLIP-FLOP IP-FLOP WITH MASTER RESET N SUFFIX CASE 648-08 PLASTIC Pinout: 16-Lead Packages (Top View) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 D SUFFIX CASE 751B-05 PLASTIC Data Inputs Clock Pulse Input Master Reset Input Outputs Outputs PIN NAMES D0 |
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Texas Instruments |
QUADRUPLE D-TYPE FLIP-FLOP complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level |
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Fairchild Semiconductor |
Quad D-Type Flip-Flop ■ ICC reduced by 50% ■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ Asynchronous common reset ■ True and complement output ■ Outputs source/sink 24mA ■ ACT175 has TTL-compatible inputs April 2007 tm General Description The |
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Toshiba Semiconductor |
Quad D-Type Flip-Flop • High speed: fmax = 170 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmissi |
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Toshiba Semiconductor |
Quad D-Type Flip-Flop • High speed: fmax = 170 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmissi |
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Toshiba |
Quad D-Type Flip Flop • High speed: fmax = 170 MHz (typ.) at VCC = 5 V • • Low power High noise idmismsiupnatitioyn: V: INCICH==8VµNAIL(m=a2x8)%atVDTCaaC=t(am2S5ihn°C)eet4U.com • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω tran |
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Toshiba |
Quad D-Type Flip-Flop • High speed: fmax = 170 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmissi |
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Hitachi Semiconductor |
Quad D-Type Flip-Flop • • • • • Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Asynchronous Common Reset True and Complement Output Outputs Source/Sink 24 mA HD74AC175 Pin Arrangement MR 1 Q0 2 Q0 3 D0 4 D1 5 Q1 6 Q1 7 GND 8 (Top view) 16 VCC 15 Q3 |
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IK Semiconductor |
Quad D-Type Flip-Flop L H H H X = Don’t care L Clock X D X H L X Outputs Q L H L Q H L H w w w .d h s a t a ee . u t4 m o c no change 1 www.DataSheet4U.com IN74AC175 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage ( |
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KODENSHI KOREA |
Quad D Flip-Flop N 16=VCC PIN 8 = GND L H H H X = Don’t care L Clock X D X H L X Outputs Q L H L Q H L H no change 1 www.DataSheet4U.com KK74AC175 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC |
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