54ACT112 डाटा शीट PDF( Datasheet )

www.DataSheet4U.com 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop September 1998 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’ACT112 contains two independent, high-speed

• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize

54ACT11253, 74ACT11253 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS040A – D3110, MARCH 1988 – REVISED APRIL 1993 • Inputs Are TTL-Voltage Compatible • 3-State Version of ′ACT1115

• Inputs Are TTL-Voltage Compatible • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND C