INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7404 5-Bit x 64-word FIFO register; 3-state Product specification Supersedes data of October 1990 File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word and bit dimensions • Pinning arranged for easy board layout: input pins directly opposite output pins • Output capability: driver (8 mA) • ICC category: LSI. APPLICATIONS • High-speed disc or tape controller • Communications buffer. GENERAL DESCRIPTION 74HC/HCT7404 The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode). With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYP. SYMBOL tPHL/tPLH fmax CI CPD Note 1. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC −1.5 V. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT7404N 74HC/HCT7404D PACKAGE PINS 18 20 PIN POSITION DIL SO20 MATERIAL plastic plastic CODE SOT102 SOT163A PARAMETER propagation delay SO, SI to DIR and DOR maximum clock frequency input capacitance power dissipation capacitance per package note 1 CONDITIONS HC CL = 15 pF; VCC = 5 V 15 30 3.5 475 HCT 17 30 3.5 490 ns MHz pF pF UNIT September 1993 2 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state PINNING (SOT102) SYMBOL OE DIR SI DO to D4 GND MR Q4 to Q0 DOR SO VCC PIN 1 2 3 9 10 11, 12, 13, 14, 15 16 17 18 DESCRIPTION output enable input (active LOW) data-in-ready output shift-in input (active HIGH) ground asynchronous master-reset input (active LOW) data outputs Q4 to Q0 data-out-ready output shift-out input (active LOW) positive supply voltage n.c. DOR n.c. VCC 12, 13, 14, 15, 16 17 18 19 20 PINNING (SOT163A) SYMBOL OE DIR SI n.c. D0 to D4 GND MR PIN 1 2 3 4 10 11 74HC/HCT7404 DESCRIPTION output enable input (active LOW) data-in-ready output shift-in input (active HIGH) not connected ground asynchronous master-reset input (active LOW) data outputs not connected data-out ready output not connected positive supply voltage 4, 5, 6, 7, 8 parallel data inputs 5, 6, 7, 8, 9 parallel data inputs handbook, halfpage handbook, halfpage OE OE DIR SI D0 D1 D2 D3 D4 GND 1 2 3 4 5 6 7 8 9 MGA670 1 2 3 4 5 18 V CC 17 SO 20 V CC 19 SO 18 DOR 17 n.c. 16 Q0 DIR SI 16 DOR n.c. 15 Q0 D0 D1 D2 D3 D4 7404 14 Q1 13 Q2 12 Q3 11 Q4 10 MR 7404 6 7 8 9 15 Q1 14 Q2 13 Q3 12 Q4 11 MR MGA671 GND 10 Fig.1 Pin configuration (SOT102). Fig.2 Pin configuration (SOT163). September 1993 3 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404 handbook, halfpage 1 (1) handbook, halfpage FIFO 64 x 5 EN4 1Z3 [IR] 3 [OR] 6 G1 G5 2 (2) 16 (18) (1) 1 OE (5) 4 (6) 5 (7) 6 (8) 7 (9) 8 D0 D1 D2 D3 D4 SI SO MR 10 (11) MGA673 Q0 Q1 Q2 Q3 Q4 DOR DIR 15 (16) 14 (15) 13 (14) 12 (13) 11 (12) (5) 4 (6) 5 (7) 6 (8) 7 (9) 8 (3) 3 (11) 10 (19) 17 CTR 1 ( /C2) CT < 64 CT = 0 CT > 0 5 5Z6 2