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R5F5110JADLF डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 32 MHz 32-bit RX MCUs - Renesas

भाग संख्या R5F5110JADLF
समारोह 32 MHz 32-bit RX MCUs
मैन्युफैक्चरर्स Renesas 
लोगो Renesas लोगो 
पूर्व दर्शन
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R5F5110JADLF pdf
RX110 Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1
Outline of Specifications (1/3)
Classification Module/Function
Description
CPU
CPU
Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per one clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit × 32-bit 64-bit
On-chip divider: 32-bit ÷ 32-bit 32 bits
Barrel shifter: 32 bits
Memory
ROM
Capacity: 8 K /16 K /32 K /64 K /96 K /128 Kbytes
32 MHz, no-wait memory access
Programming/erasing method:
Serial programming (asynchronous serial communication), self-programming
RAM
Capacity: 8 K /10 K /16 Kbytes
32 MHz, no-wait memory access
MCU operating mode
Single-chip mode
Clock
Clock generation circuit
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
and IWDT-dedicated on-chip oscillator
Oscillation stop detection: Available
Clock frequency accuracy measurement circuit (CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,
64).
Resets
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
Voltage detection Voltage detection circuit
(LVDAa)
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Low power
consumption
Low power consumption
functions
Module stop function
Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Function for lower operating Operating power control modes
power consumption
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt
Interrupt controller (ICUb)
Interrupt vectors: 65
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt,
and IWDT interrupt)
16 levels specifiable for the order of priority
DMA
Data transfer controller
(DTCa)
Transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
R01DS0202EJ0110 Rev.1.10
Dec 10, 2014
Page 2 of 103

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