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PL585-28 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 19MHz to 250MHz Low Phase-Noise VCXO - Micrel

भाग संख्या PL585-28
समारोह 19MHz to 250MHz Low Phase-Noise VCXO
मैन्युफैक्चरर्स Micrel 
लोगो Micrel लोगो 
पूर्व दर्शन
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<?=PL585-28?> डेटा पत्रक पीडीएफ

PL585-28 pdf
DIE SPECIFICATIONS
1.65mm
8
9
Die ID
Y
10
X
11 0,0
12
13
14
(Preliminary) PL585-28
19MHz to 250MHz Low Phase-Noise VCXO
7 Chip size, active area 1.650mm x 2.250mm
Chip thickness
200µm ± 20µm
6
5
PAD size
80µm x 80µm
4
Scribe Line Dimension
X = 80µm
Y = 80µm
Chip Base
GND level
Die ID:
3
PL585-28DC
C685B C9-99-99-9
2
1
SCRIBE LINE
PAD ASSIGNMENT AND DESCRIPTION (The X/Y coordinates indicate pad centers)
Name
Pad # X (m) Y (m)
Description
Q
VDD_BUF
QB
VDD_BUF
VDD_DIG
VDD_ANA
XOUT
XIN
VCON/SCLK
1
2
3
4
5
6
7
8
9
OE/PDB/SDIO 10
DNC
GND_ANA
GND_DIG
GND_BUF
11
12
13
14
+726
+726
+726
+726
+726
+726
+678
-195
-726
-726
-726
-726
-726
-726
-905
-677
-449
+265
+427
+665
+1031
+1031
+935
+131
-155
-425
-593
-761
Output buffer
VDD connection for buffer circuitry
Output buffer
VDD connection for buffer circuitry
VDD connection for digital circuitry
VDD connection for analog circuitry
Output connection to crystal
Crystal input connection
Analog voltage pin for the VCXO. The serial interface uses this
pin for the serial clock input (SCLK), during programming.
This pin may be programmed as output enable (OE), or power-
down (PDB) pin.
The serial interface uses this pin for the serial data input (SDIO)
during programming. This pin incorporates an Internal pull -up
resistor of 60Kfor OE, PDB operations.
Do not connect
GND connection for analog circuitry
GND connection for digital circuitry
GND connection for buffer circuitry
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/16/11 Page 2

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डाउनलोड[ PL585-28 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
PL585-2819MHz to 250MHz Low Phase-Noise VCXOMicrel
Micrel


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