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A3R1GE40JBF डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 1Gb DDRII Synchronous DRAM - Zentel

भाग संख्या A3R1GE40JBF
समारोह 1Gb DDRII Synchronous DRAM
मैन्युफैक्चरर्स Zentel 
लोगो Zentel लोगो 
पूर्व दर्शन
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A3R1GE40JBF pdf
A3R1GE30JBF
A3R1GE40JBF
1Gb DDRII Synchronous DRAM
Specifications
Features
Density: 1G bits
Organization
16M words × 8 bits × 8 banks (A3R1GE30JBF)
8M words × 16 bits × 8 banks (A3R1GE40JBF)
Package
60-ball FBGA(μBGA) (A3R1GE30JBF)
84-ball FBGA(μBGA) (A3R1GE40JBF)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Data rate: 1066Mbps/800Mbps (max.)
1KB page size (A3R1GE30JBF)
Row address: A0 to A13
Column address: A0 to A9
2KB page size (A3R1GE40JBF)
Row address: A0 to A12
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5, 6, 7
Recharge: auto recharge option for each burst access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8μs at TC+85°C
3.9μs at TC+85°C
Industrial grade compliant with AEC-Q100 grade3
Automotive grade compliant with AEC-Q100 grade2
Operating case temperature range
TC = 0°C to +95°C (Commercial grade)*
TC = -40°C to +95°C (Industrial grade)*
TC = -40°C to +105°C (Automotive grade)*
Double-data-rate architecture; two data transfers per clock
cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is
transmitted/received with data for capturing data at the
receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die-Termination for better signal quality
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
Off-Chip Driver (OCD) impedance adjustment is not
supported
Note: Refer to operating temperature condition on page 5 for
details
Zentel Electronics Corporation reserve the right to change products or specification without notice.
Revision 1.0
Page 1 / 72
Dec., 2014

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
A3R1GE40JBF1Gb DDRII Synchronous DRAMZentel
Zentel


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