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A3S64D40GTP डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 64M Double Data Rate Synchronous DRAM - Zentel

भाग संख्या A3S64D40GTP
समारोह 64M Double Data Rate Synchronous DRAM
मैन्युफैक्चरर्स Zentel 
लोगो Zentel लोगो 
पूर्व दर्शन
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A3S64D40GTP pdf
A3S64D40GTP
64M Double Data Rate Synchronous DRAM
DESCRIPTION
A3S64D40GTP is a 4-bank x 1,048,576-word x 16bit double data rate synchronous DRAM , with
SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data
is registered on both edges of data strobe ,and output data and data strobe are referenced on both
edges of CLK. The A3S64D40GTP achieves very high speed clock rate up to 200 MHz .
FEATURES
- Vdd=VddQ=2.5V+0.2V (-50)
- Double data rate architecture ; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock input (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- Commands entered on each positive CLK edge
- Data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- CAS latency - 2 / 2.5 / 3 (programmable)
- Burst length - 2 / 4 / 8 (programmable)
- Burst type - Sequential / Interleave (programmable)
- Auto Precharge / All Bank Precharge controlled by A10
- Support concurrent Auto Precharge
- 4096 refresh cycles / 64ms (4 banks concurrent refresh)
- Auto Refresh and Self Refresh
- Row address A0-11 / Column address A0-7
- SSTL_2 Interface
- Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch
Zentel Electronics Corporation reserve the right to change products or specification without notice.
Revision 1.0
Page 1/ 39
Nov., 2012

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
A3S64D40GTP64M Double Data Rate Synchronous DRAMZentel
Zentel


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