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NB3M8302C डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V 200 MHz 1:2 LVCMOS/LVTTL Low Skew Fanout Buffer - ON Semiconductor

भाग संख्या NB3M8302C
समारोह 3.3V 200 MHz 1:2 LVCMOS/LVTTL Low Skew Fanout Buffer
मैन्युफैक्चरर्स ON Semiconductor 
लोगो ON Semiconductor लोगो 
पूर्व दर्शन
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<?=NB3M8302C?> डेटा पत्रक पीडीएफ

NB3M8302C pdf
NB3M8302C
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Number Name
1, 6 VDDO
2 VDD
3 CLK
4, 7 GND
5 Q1
8 Q0
Type
Output Power
Input and Core Power
LVCMOS/LVTTL Input
Ground
LVCMOS/LVTTL Output
LVCMOS/LVTTL Output
Description
Clock output Supply pin.
Input and Core Supply pin.
Clock Input. Internally pull−down.
Supply Ground.
LVCMOS/LVTTL Clock output.
LVCMOS/LVTTL Clock output.
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition
Min Max Unit
VDD, VDDO
VI
Tstg
qJA
Power Supply
Input Voltage
Storage Temperature
Thermal Resistance (Junction to Ambient)
SOIC−8
0 lfpm
500 lfpm
− 4.6 V
−0.5 VDD + 0.5 V V
−65
+150
_C
_C/W
80
55
qJC Thermal Resistance (Junction to Case)
(Note 1)
12−17
_C/W
Tsol
MSL
Wave Solder
Moisture Sensitivity
SOIC−8
3 sec
265 _C
Indefinite Time Out of Drypack
(Note 2)
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power)
2. For additional information, see Application Note AND8003/D.
www.onsemi.com
2

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भाग संख्याविवरणविनिर्माण
NB3M8302C3.3V 200 MHz 1:2 LVCMOS/LVTTL Low Skew Fanout BufferON Semiconductor
ON Semiconductor


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