DataSheet.in

NB6L14S डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator - ON Semiconductor

भाग संख्या NB6L14S
समारोह 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator
मैन्युफैक्चरर्स ON Semiconductor 
लोगो ON Semiconductor लोगो 
पूर्व दर्शन
1 Page
		
<?=NB6L14S?> डेटा पत्रक पीडीएफ

NB6L14S pdf
NB6L14S
Q0 Q0 VCC GND
16 15 14 13
Exposed Pad (EP)
Q1 1
Q1 2
Q2 3
Q2 4
NB6L14S
12 IN
11 VT
10 VREFAC
9 IN
5 678
Q3 Q3 VCC EN
Figure 3. NB6L14S Pinout, 16pin QFN (Top View)
Table 1. TRUTH TABLE
IN IN EN Q
01 1 0
10 1 1
xx
0 0 (Note 1)
1. On next transition of the input signal (IN).
Q
1
0
1 (Note 1)
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1 Q1
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2 Q1
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3 Q2
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4 Q2
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5 Q3
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
6 Q3
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
7 VCC
Positive Supply Voltage.
8 EN LVTTL / LVCMOS Input Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 26. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML, LVDS
Inverted Differential Input
10 VREFAC
LVPECL Output
The VREFAC reference output can only be used to rebias capacitorcoupled
differential or singleended input signals. For the capacitorcoupled IN and/or
INb inputs, VREFAC should be connected to the VT pin and bypassed to ground
with a 0.01 mF capacitor.
11 VT
LVPECL Output
Internal 100 W Centertapped Termination Pin for IN and IN
12
IN
LVPECL, CML, LVDS
Noninverted Differential Input. (Note 2)
13 GND
Negative Supply Voltage.
14 VCC
15 Q0
LVDS Output
Positive Supply Voltage.
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
16 Q0
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heatsinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to selfoscillation.
http://onsemi.com
2

विन्यास 11 पेज
डाउनलोड[ NB6L14S Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
NB6L14Differential 1:4 LVPECL Fanout BufferON Semiconductor
ON Semiconductor
NB6L14MDifferential 1:4 CML Fanout BufferON Semiconductor
ON Semiconductor


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English