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NB3N853501E डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 3.3V LVTTL/LVCMOS 2:1 MUX to 4 LVPECL Differential Clock Fanout Buffer Outputs - ON Semiconductor

भाग संख्या NB3N853501E
समारोह 3.3V LVTTL/LVCMOS 2:1 MUX to 4 LVPECL Differential Clock Fanout Buffer Outputs
मैन्युफैक्चरर्स ON Semiconductor 
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NB3N853501E pdf
NB3N853501E
VEE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
VCC
1
2
3
4
5
6
7
8
9
10
20 Q0
19 Q0
18 VCC
17 Q1
16 Q1
15 Q2
14 Q2
13 VCC
12 Q3
11 Q3
Figure 2. Pinout Diagram (Top View)
Table 1. PIN DESCRIPTION
Number
1
2
Name
VEE
CLK_EN
3 CLK_SEL
4 CLK0
5, 6, 8, 9
6
nc
CLK1
10, 13, 18
11, 14, 16,
19
12, 15, 16,
20
VCC
Q[3:0]
Q[3:0]
I/O
LVCMOS /
LVTTL
LVCMOS /
LVTTL
LVCMOS /
LVTTL
LVCMOS /
LVTTL
LVPECL
LVPECL
Open
Default
Pullup
Pulldown
Description
Negative (Ground) Power Supply pin must be externally connected to
power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
Clock Input Select (HIGH selects CLK1, LOW selects CLK0 input)
Pulldown Clock 0 Input. Float open when unused.
Pulldown
No Connect
Clock 1 Input. Float open when unused.
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Invert Differential Outputs
True Differential Outputs
Table 2. FUNCTIONS
Inputs
Outputs
CLK_EN
CLK_SEL
Input Function
Output Function
Qx Qx
0 0 CLK0 input selected
Disabled
LOW
HIGH
0 1 CLK1 Input Selected
Disabled
LOW
HIGH
1 0 CLK0 input selected
Enabled
CLK0
Invert of
CLK1
1 1 CLK1 Input Selected
Enabled
CLK1
Invert of
CLK1
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
http://onsemi.com
2

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भाग संख्याविवरणविनिर्माण
NB3N853501E3.3V LVTTL/LVCMOS 2:1 MUX to 4 LVPECL Differential Clock Fanout Buffer OutputsON Semiconductor
ON Semiconductor


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