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NB3M8T3910G डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 2.5V/3.3V 3:1:10 Configurable Differential Clock Fanout Buffer - ON Semiconductor

भाग संख्या NB3M8T3910G
समारोह 2.5V/3.3V 3:1:10 Configurable Differential Clock Fanout Buffer
मैन्युफैक्चरर्स ON Semiconductor 
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NB3M8T3910G pdf
VDD
GND
BANK A
SMODEA0
SMODEA1
SEL0
SEL1
CLK0
CLK0
CLK1
CLK1
XTAL_IN
XTAL_OUT
IREF
SMODEB0
SMODEB1
CONTROL
3:1
Mux
OSC
CONTROL
BANK B
OE_SE
SYNC
Figure 1. Simplified Logic Diagram
NB3M8T3910G
VDDOA
QA0
QA0
QA1
QA1
QA2
QA2
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
QB2
QB2
QB3
QB3
QB4
QB4
Exposed
Pad (EP)
QA0 1
QA0 2
QA1 3
QA1 4
VDDOA 5
QA2 6
QA2 7
VDDOA 8
QA3 9
QA3 10
QA4 11
QA4 12
48 47 46 45 44 43 42 41 40 39 38 37
NB3M8T3910G
13 14 15 16 17 18 19 20 21 22 23 24
36 QB0
35 QB0
34 QB1
33 QB1
32 VDDOB
31 QB2
30 QB2
29 VDDOB
28 QB3
27 QB3
26 QB4
25 QB4
VDDOB
VDDOC
REFOUT
Figure 2. QFN−48 Pinout Configuration
(Top View)
Table 1. PIN DESCRIPTION
Number
1, 2
3, 4
5, 8
Name
QA0, QA0
QA1, QA1
VDDOA
Type
Output
Output
Power
29, 32
VDDOB
Power
45
VDDOC
Power
6,7
9,10
11,12
13, 18,
24, 37,
43, 48
14, 47
QA2, QA2
QA3, QA3
QA4, QA4
GND
Output
Output
Output
Power
SMODEA0 /
SMODEA1
Input
Default
(Internal
Resistors)
Pulldown
Description
Bank A differential output pair Q0. Configurable as LVPECL / LVDS / HCSL
Bank A differential output pair Q1. Configurable as LVPECL / LVDS / HCSL
VDDOA Positive Supply pin for Bank A outputs. VDDOA pins must all be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01 mF cap to GND
VDDOB Positive Supply pin for Bank B outputs. VDDOB pins must all be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01 mF cap to GND
VDDOC Positive Supply pin for REFOUT output. VDDOC pin must be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01 mF cap to GND
Bank A differential output pair Q2. Configurable as LVPECL / LVDS / HCSL.
Bank A differential output pair Q3. Configurable as LVPECL / LVDS / HCSL
Bank A differential output pair Q4. Configurable as LVPECL / LVDS / HCSL
Ground Supply. All GND pins must be externally connected to power supply
to guarantee proper operation.
Output driver selectors for BANK A. See Table 6 for function.
LVCMOS/LVTTL levels.
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NB3M8T3910G2.5V/3.3V 3:1:10 Configurable Differential Clock Fanout BufferON Semiconductor
ON Semiconductor


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