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NB3N3020 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - LVPECL/LVCMOS Clock Multiplier - ON Semiconductor

भाग संख्या NB3N3020
समारोह LVPECL/LVCMOS Clock Multiplier
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<?=NB3N3020?> डेटा पत्रक पीडीएफ

NB3N3020 pdf
527 MHz Crystal
or
2 – 210 MHz Clock
X1 / CLK
X2
NB3N3020
VDD
GND
OE2
Clock
Buffer/
Crystal
Oscillator
Pre
Slecra
Phase
Detector
Loop Filter
VCO
%N
Select Control Block
Sel0 Sel1 Sel2
Figure 1. NB3N3020 Simplified Logic Diagram
LVPECL
Output
LVCMOS/
LVTTL
Output
CLK2
CLK2
CLK1
OE1
Table 1. PIN DESCRIPTION
Pin Name
I/O
6
Sel0
TriLevel Input
5
Sel1
TriLevel Input
4
Sel2
TriLevel Input
1, 11, 15
2
VDD
X1/CLK
Power Supply
Input
3 X2
Input
7
16
8, 9, 12
13
14
10
OE1
OE2
GND
CLK2
CLK2
CLK1
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
Power Supply
LVPECL Output
LVPECL Output
LVTTL/ LVCMOS
Output
Description
Frequency select input 0. When left open, defaults to VDD/ 2. See output select Table 2
for details.
Frequency select input 1. When left open, defaults to VDD/ 2. See output select Table 2
for details.
Frequency select input 2. When left open, defaults to VDD/ 2. See output select Table 2
for details.
Positive supply voltage pins are connected to +3.3 V supply voltage.
Crystal or Clock input. Connect to 5 27 MHz crystal source or 2 – 210 MHz single
ended clock. See Table 2.
Crystal input. Connect to a 5 – 27 MHz crystal or leave unconnected for clock input. See
Table 2.
Output enable input that synchronously tristates CLK1 output when low. Internal pullup
resistor to VDD.
Output enable input that when LOW synchronously controls LVPECL outputs by forcing
CLK2 LOW and CLK2 HIGH. Internal pullup resistor to VDD.
Ground 0 V. These pins provide GND return path for the devices.
Inverted clock output. Clock frequency equals input frequency times multiplier.
Noninverted clock output. Clock frequency equals input frequency times multiplier.
Clock Output. Clock frequency equals input frequency times multiplier.
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भाग संख्याविवरणविनिर्माण
NB3N3020LVPECL/LVCMOS Clock MultiplierON Semiconductor
ON Semiconductor


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