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TH58TEG8DDKTAK0 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - NAND memory Toggle DDR1.0 - Toshiba

भाग संख्या TH58TEG8DDKTAK0
समारोह NAND memory Toggle DDR1.0
मैन्युफैक्चरर्स Toshiba 
लोगो Toshiba लोगो 
पूर्व दर्शन
1 Page
		
<?=TH58TEG8DDKTAK0?> डेटा पत्रक पीडीएफ

TH58TEG8DDKTAK0 pdf
TOSHIBA CONFIDENTIAL Tx58TEGxDDKTAx0
CONTENTS
1. INTRODUCTION ............................................................................................................................................. 7
1.1. General Description...................................................................................................................................... 7
1.2. Definitions and Abbreviations...................................................................................................................... 7
1.3. Features ........................................................................................................................................................ 9
1.4. Diagram Legend.......................................................................................................................................... 10
2. PHYSICAL INTERFACE................................................................................................................................ 11
2.1. Pin Descriptions.......................................................................................................................................... 11
2.2. PIN ASSIGNMENT (TOP VIEW) .............................................................................................................. 12
2.3. BLOCK DIAGRAM ..................................................................................................................................... 13
2.4. Independent Data Buses ............................................................................................................................ 16
2.5. Absolute Maximum DC Rating .................................................................................................................. 16
2.6. Operating Temperature Condition............................................................................................................. 17
2.7. Recommended Operating Conditions......................................................................................................... 17
2.8. Valid Blocks................................................................................................................................................. 17
2.9. AC Overshoot/Undershoot Requirements.................................................................................................. 18
2.10. DC Operating Characteristics.................................................................................................................... 19
2.11. Input/Output Capacitance (TOPER =25, f=1MHz) ................................................................................... 21
2.12. DQ Driver Strength .................................................................................................................................... 22
2.13. Input/Output Slew rate .............................................................................................................................. 24
2.14. High Speed Toggle DDR with ODT ............................................................................................................ 26
2.14.1. ODT (On die termination) ...................................................................................................................... 26
2.14.2. ODT setting............................................................................................................................................. 26
2.14.3. ODT behavior during Read operation.................................................................................................... 26
2.14.4. ODT behavior during Write operation................................................................................................... 27
2.14.5. Functional Representation of ODT ........................................................................................................ 27
2.15. R/ B and SR[6] Relationship..................................................................................................................... 28
2.16. Write Protect ............................................................................................................................................... 28
3. MEMORY ORGANIZATION .......................................................................................................................... 29
3.1. Addressing................................................................................................................................................... 30
3.1.1. Plane Addressing .................................................................................................................................... 30
3.1.2. Extended Blocks Arrangement............................................................................................................... 31
3.2. Factory Defect Mapping ............................................................................................................................. 32
3.2.1. Device Requirements.............................................................................................................................. 32
3.2.2. Host Requirements ................................................................................................................................. 33
4. FUNCTION DESCRIPTION .......................................................................................................................... 34
4.1. Discovery and Initialization ....................................................................................................................... 34
4.1.1. Power-on/off sequence............................................................................................................................. 34
4.1.2. VPP Initialization..................................................................................................................................... 35
4.1.3. Single Channel Discovery....................................................................................................................... 35
4.1.4. Dual Channel Discovery......................................................................................................................... 35
4.2. Mode Selection ............................................................................................................................................ 36
4.2.1. Toggle DDR1.0 General Timing ............................................................................................................. 37
4.2.1.1. Command Latch Cycle............................................................................................................................ 37
4.2.1.2. Address Latch Cycle ............................................................................................................................... 37
4.2.1.3. Basic Data Input Timing ........................................................................................................................ 38
4.2.1.4. Basic Data Output Timing ..................................................................................................................... 39
4.2.1.5. Read ID Operation.................................................................................................................................. 40
4.2.1.6. Status Read Cycle................................................................................................................................... 41
4.2.1.7. Set Feature.............................................................................................................................................. 42
4.2.1.8. Get Feature ............................................................................................................................................. 42
4.2.1.9. Page Read Operation.............................................................................................................................. 43
4.2.1.10. Page Program Operation.................................................................................................................... 45
4.2.2. SDR General Timing .............................................................................................................................. 46
4.2.2.1. Command Latch Cycle............................................................................................................................ 46
4.2.2.2. Address Latch Cycle ............................................................................................................................... 46
4.2.2.3. Basic Data Input Timing ........................................................................................................................ 47
4.2.2.4. Basic Data Output Timing ..................................................................................................................... 47
4.2.2.5. Read ID Operation.................................................................................................................................. 48
4.2.2.6. Status Read Cycle................................................................................................................................... 49
TC58TEG6DDKTA00 / TC58TEG6DDKTAI0
TH58TEG7DDKTA20 / TH58TEG7DDKTAK0
TH58TEG8DDKTA20 / TH58TEG8DDKTAK0
1
TENTATIVE 2013-07-10C

विन्यास 30 पेज
डाउनलोड[ TH58TEG8DDKTAK0 Datasheet.PDF ]


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TH58TEG8DDKTAK0NAND memory Toggle DDR1.0Toshiba
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