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AT45DB321D डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 2.5V or 2.7V DataFlash - Adesto

भाग संख्या AT45DB321D
समारोह 2.5V or 2.7V DataFlash
मैन्युफैक्चरर्स Adesto 
लोगो Adesto लोगो 
पूर्व दर्शन
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<?=AT45DB321D?> डेटा पत्रक पीडीएफ

AT45DB321D pdf
1. Description
The AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of digital
voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the RapidS serial interface for
applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up to 66MHz.
The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory,
the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data while a
page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM (electrically
erasable and programmable read-only memory) emulation (bit or byte alterability) is easily handled with a self-contained,
three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with multiple
address lines and a parallel interface, DataFlash® devices use a RapidS serial interface to sequentially access its data. The
simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability,
minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial
applications where high density, low pin count, low voltage and low power are essential.
To allow for simple, in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The
device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is
enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the serial input (SI), serial output
(SO), and serial clock (SCK) lines.
All programming and erase cycles are self timed.
Figure 1-1. Pin configurations and pinouts.
MLF(1) (VDFN)
Top View
SOIC
Top View
SI 1
SCK 2
RESET 3
CS 4
8 SO
7 GND
6 VCC
5 WP
Note:
1. The metal pad on the bottom of
the MLF package is floating.
This pad can be a “No Connect” or
connected to GND.
BGA Package Ball-out
Top View
SI
SCK
RESET
CS
1
2
3
4
8 SO
7 GND
6 VCC
5 WP
TSOP: Type 1
Top View
12 3 4 5
A
NC NC NC NC
B
NC SCK GND VCC NC
C
NC CS RDY/BSY WP NC
D
NC SO
SI RESET NC
E
NC NC NC NC NC
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
Note:
TSOP package is not recommended for new designs.
Future die shrinks will support 8-pin packages only.
AT45DB321D [DATASHEET]
3597T–DFLASH–11/2013
2

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