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AT25DN256 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 2.3V Minimum SPI Serial Flash Memory - Adesto

भाग संख्या AT25DN256
समारोह 2.3V Minimum SPI Serial Flash Memory
मैन्युफैक्चरर्स Adesto 
लोगो Adesto लोगो 
पूर्व दर्शन
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<?=AT25DN256?> डेटा पत्रक पीडीएफ

AT25DN256 pdf
1. Description
The Adesto® AT25DN256 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer
based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DN256, with its page erase granularity it is ideal for data storage as well, eliminating the
need for additional data storage devices.
The erase block sizes of the AT25DN256 have been optimized to meet the needs of today's code and data storage applications.
By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules
and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that
occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device
density.
The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as
unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in many different systems, the AT25DN256 supports read, program, and erase operations with a
wide supply voltage range of 2.3V to 3.6V. No separate voltage is required for programming and erasing.
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol
CS
SCK
SI (I/O0)
SO
(I/O1)
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched in on the rising
edge of SCK.
With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O0) in conjunction with
other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the SI (I/O0) pin will be referenced as the SI
pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O0.
Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O1) in conjunction with
other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as the SO
pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O1.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
Asserted
State
Low
-
-
-
Type
Input
Input
Input/
Output
Input/
Output
AT25DN256
DS-25DN256–039B–5/2014
2

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