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LMK04800 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Low-Noise Clock Jitter Cleaner - National Semiconductor

भाग संख्या LMK04800
समारोह Low-Noise Clock Jitter Cleaner
मैन्युफैक्चरर्स National Semiconductor 
लोगो National Semiconductor लोगो 
पूर्व दर्शन
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<?=LMK04800?> डेटा पत्रक पीडीएफ

LMK04800 pdf
LMK048XX EVALUATION BOARD OPERATING INSTRUCTIONS
Table of Contents
TABLE OF CONTENTS.............................................................................................................................................. 2
GENERAL DESCRIPTION.......................................................................................................................................... 4
EVALUATION BOARD KIT CONTENTS ..................................................................................................................................4
AVAILABLE LMK048XX EVALUATION BOARDS.....................................................................................................................4
AVAILABLE LMK04800 FAMILY DEVICES ...........................................................................................................................4
QUICK START ......................................................................................................................................................... 5
DEFAULT CODELOADER MODES FOR EVALUATION BOARDS....................................................................................................6
EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04808B ........................................................................... 7
1. START CODELOADER 4 APPLICATION..............................................................................................................................7
2. SELECT DEVICE ..........................................................................................................................................................7
3. PROGRAM/LOAD DEVICE.............................................................................................................................................8
4. RESTORING A DEFAULT MODE......................................................................................................................................8
5. VISUAL CONFIRMATION OF FREQUENCY LOCK..................................................................................................................9
6. ENABLE CLOCK OUTPUTS.............................................................................................................................................9
PLL LOOP FILTERS AND LOOP PARAMETERS......................................................................................................... 11
PLL 1 LOOP FILTER ......................................................................................................................................................11
122.88 MHz VCXO PLL ........................................................................................................................................11
PLL2 LOOP FILTER .......................................................................................................................................................12
Integrated VCO PLL ............................................................................................................................................12
EVALUATION BOARD INPUTS AND OUTPUTS....................................................................................................... 13
RECOMMENDED TEST EQUIPMENT...................................................................................................................... 21
PROGRAMMING 0-DELAY MODE IN CODELOADER .............................................................................................. 22
OVERVIEW..................................................................................................................................................................22
DUAL LOOP 0-DELAY MODE EXAMPLES ...........................................................................................................................22
Programming Steps............................................................................................................................................22
Details ................................................................................................................................................................22
SINGLE LOOP 0-DELAY MODE EXAMPLES .........................................................................................................................24
Programming Steps............................................................................................................................................24
Details ................................................................................................................................................................24
APPENDIX A: CODELOADER USAGE...................................................................................................................... 26
PORT SETUP TAB .........................................................................................................................................................26
CLOCK OUTPUTS TAB ...................................................................................................................................................27
PLL1 TAB...................................................................................................................................................................29
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency.......................................................................30
PLL2 TAB...................................................................................................................................................................31
BITS/PINS TAB ............................................................................................................................................................32
REGISTERS TAB............................................................................................................................................................37
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS................................................................................. 38
PLL1 .........................................................................................................................................................................38
122.88 MHz VCXO Phase Noise ..........................................................................................................................38
Clock Output Measurement Technique..............................................................................................................39
Buffered OSCout Phase Noise.............................................................................................................................39
2
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