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MX25L51245G डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - FLASH MEMORY - MACRONIX

भाग संख्या MX25L51245G
समारोह FLASH MEMORY
मैन्युफैक्चरर्स MACRONIX 
लोगो MACRONIX लोगो 
पूर्व दर्शन
1 Page
		
<?=MX25L51245G?> डेटा पत्रक पीडीएफ

MX25L51245G pdf
PRELIMINARY
MX25L51245G
Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 6
Table 1. Read performance Comparison.....................................................................................................6
3. PIN CONFIGURATIONS .......................................................................................................................................... 7
4. PIN DESCRIPTION................................................................................................................................................... 7
5. BLOCK DIAGRAM.................................................................................................................................................... 8
6. DATA PROTECTION................................................................................................................................................. 9
Table 2. Protected Area Sizes....................................................................................................................10
Table 3. 4K-bit Secured OTP Definition..................................................................................................... 11
7. Memory Organization............................................................................................................................................ 12
Table 4. Memory Organization...................................................................................................................12
8. DEVICE OPERATION............................................................................................................................................. 13
8-1. 256Mb Address Protocol........................................................................................................................... 15
8-2. Quad Peripheral Interface (QPI) Read Mode........................................................................................... 18
9. COMMAND DESCRIPTION.................................................................................................................................... 19
Table 5. Command Set...............................................................................................................................19
9-1. Write Enable (WREN)............................................................................................................................... 24
9-2. Write Disable (WRDI)................................................................................................................................ 25
9-3. Read Identification (RDID)........................................................................................................................ 26
9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 27
9-5. Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 29
9-6. QPI ID Read (QPIID)................................................................................................................................ 30
Table 6. ID Definitions ...............................................................................................................................30
9-7. Read Status Register (RDSR).................................................................................................................. 31
9-8. Read Configuration Register (RDCR)....................................................................................................... 32
9-9. Write Status Register (WRSR).................................................................................................................. 38
Table 7. Protection Modes..........................................................................................................................39
9-10. Enter 4-byte mode (EN4B)....................................................................................................................... 42
9-11. Exit 4-byte mode (EX4B).......................................................................................................................... 42
9-12. Read Data Bytes (READ)......................................................................................................................... 43
9-13. Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 44
9-14. Dual Output Read Mode (DREAD)........................................................................................................... 45
9-15. 2 x I/O Read Mode (2READ).................................................................................................................... 46
9-16. Quad Read Mode (QREAD)..................................................................................................................... 47
9-17. 4 x I/O Read Mode (4READ).................................................................................................................... 48
9-18. Fast Double Transfer Rate Read (FASTDTRD)........................................................................................ 50
9-19. 2 x I/O Double Transfer Rate Read Mode (2DTRD)................................................................................. 51
9-20. 4 x I/O Double Transfer Rate Read Mode (4DTRD)................................................................................. 52
9-21. Preamble Bit ............................................................................................................................................ 54
9-22. 4 Byte Address Command Set.................................................................................................................. 59
9-23. Performance Enhance Mode.................................................................................................................... 65
9-24. Performance Enhance Mode Reset.......................................................................................................... 70
P/N: PM2006
REV. 0.01, JAN. 06, 2014
2
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