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AN6-206 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Primary-Side Synchronous Rectifier (SR) Trigger Solution - Fairchild Semiconductor

भाग संख्या AN6-206
समारोह Primary-Side Synchronous Rectifier (SR) Trigger Solution
मैन्युफैक्चरर्स Fairchild Semiconductor 
लोगो Fairchild Semiconductor लोगो 
पूर्व दर्शन
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<?=AN6-206?> डेटा पत्रक पीडीएफ

AN6-206 pdf
AN-6206
1. FAN6210 External Component Setting
Figure 2 and Figure 3 show the simplified schematic of two
switch forward converters and their waveforms. The
rectifying SR (SR1) should be turned on right after the
primary-side MOSFETs are turned on. Then, SR1 should be
turned off right before the primary-side MOSFETs are
turned off. The freewheeling SR (SR2) should be turned on
right after the primary-side MOSFETs are turned off. Then,
SR2 should be turned off right before the primary-side
MOSFETs are turned on. The primary-side SR trigger
controller FAN6210 generates XN and XP signals, where
XN rising edge triggers the turn-off of SR and XP rising
edge triggers the turn-on of SR. FAN6210 generates XP and
XN signals two times for each in one switching cycle and
FAN6206 in the secondary side determines which SR
MOSFET should be controlled for each XP and XN signals
within one switching cycle.
APPLICATION NOTE
Figure 4 and Figure 5 show the detailed timing diagrams of
XP and XN for the rising edge and falling edge of the SIN
signal. The delay from the rising edge of SOUT to XP
signal rising edge (tDLY_XP) is programmable using R1, as
shown in Figure 1. The linear relationship between R1 and
tDLY_XP is shown in Figure 6.
The transformer winding voltage is much higher than the
voltage rating of FAN6210 during PWM turn-on time.
Therefore, R2 and D1 are used to block the high voltage, as
shown in Figure 1. Since there is a 400ns DET falling-edge
detection window after SOUT falls to prevent mis-
triggering of XP in DCM operation, too large value of R2
does not trigger XP properly due to too large RC time
delay. It is typical to use 10k~33kfor R2.
The other requirement for triggering XP signal is that the
HIGH level of the DET signal must be higher than 3V. To
shorten the falling time from HIGH level to LOW level,
the breakdown voltage of Zener diode D2 is recommended
as 5~6V.
Figure 2. Simplified Circuit Diagram of
Dual-Forward Converter
Figure 4. Timing Diagram During PWM Rising Edge
Figure 3. Key Waveforms of Dual-Forward Converter
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
2
Figure 5. Timing Diagram During PWM Falling Edge
www.fairchildsemi.com
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भाग संख्याविवरणविनिर्माण
AN6-206Primary-Side Synchronous Rectifier (SR) Trigger SolutionFairchild Semiconductor
Fairchild Semiconductor


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