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R8A66156SP डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 24-bit I/O EXPANDER - Renesas

भाग संख्या R8A66156SP
समारोह 24-bit I/O EXPANDER
मैन्युफैक्चरर्स Renesas 
लोगो Renesas लोगो 
पूर्व दर्शन
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R8A66156SP pdf
R8A66156SP
BLOCK DIAGRAM
Vcc Vcc
48
CLK 5
S9
CS 7
DI 3
Shift register 1 DO
D24 D23 D22
D3 D2 D1
2 DO
36 D1
35 D2
34 D3
Q24 Q23 Q22
Q3 Q2 Q1
Parallel output latch
D24 D23 D22
D3 D2 D1
Q24 Q23 Q22
Q3 Q2 Q1
DI Shift register 2
13 D22
12 D23
11 D24
1 6 10 19 28
GND GND GND GND GND
Vcc
CLK, S, CS, DI
S
Input type
Vcc Vcc
DO D1D24
Output
Inout
Output Type
FUNCTION
The R8A66156 is produced by using the silicon gate CMOS technology and has low power dissipation and
high noise margin.
Built in two shift registers for serial in-parallel out (Shift register 2) and parallel in-serial out (Shift register 1)
are constructed independently, R8A66156 is able to read serial input data into a shift register while output
the serial data converting from the parallel data input.
Serial output operation of 24-bit parallel latched data and serial input operation from MCU are started when
/CS is changed from "H" to "L".
24-bit parallel data are latched by the negative edge of /CS and are output from the DO terminal
synchronously to the negative edge of CLK, and also the DI terminal read serial input data from MCU and
are written into the internal shift register 2.
The 25th and following shift clock pulse are ignored and serial input data is masked, and DO terminal
becomes high-impedance ("High-Z").
When /CS is changed from "L" to "H", 24-bit serial data which is read from the DI terminal are output to the
D1~D24 terminals as parallel data.
As the output circuit type of D1~D24 terminals is N-ch open drain output, write data "H" for pins which should
be set to input mode.
REJ03F0283-0100 Rev.1.00 Sep.14.2009
Page 2 of 7
.
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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
R8A66156SP24-bit I/O EXPANDERRenesas
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