TDA10023HT डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - Single chip DVB-C/MCNS channel receiver - Philips

भाग संख्या TDA10023HT
समारोह Single chip DVB-C/MCNS channel receiver
मैन्युफैक्चरर्स Philips 
लोगो Philips लोगो 
पूर्व दर्शन
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TDA10023HT pdf
Philips Semiconductors
Single chip DVB-C/MCNS channel receiver
2. Features
s 4,16, 32, 64, 128 and 256 QAM demodulator (ITU-T J.83 annex A-B and C compatible)
s High performance for 256 QAM especially for direct IF applications
s On-chip 10-bit ADC
s On-chip PLL for crystal frequency multiplication (typically 16 MHz crystal)
s Digital down conversion
s Programmable half Nyquist filter (roll off = 0.12, 0.13, 0.15 and 0.18)
s Two PWM AGC outputs with programmable take-over point (for tuner and down
converter control)
s Clock timing recovery, with programmable second order loop filter
s Variable symbol rate capability from SACLK/64 to SACLK/4 (with low sampling clock:
SACLK = 36 MHz maximum) or from SACLK/128 to SACLK/8 (with high sampling
clock: SACLK = 72 MHz maximum)
s Programmable anti-aliasing filters
s Full digital carrier recovery loop
s Carrier acquisition range up to 9 % of symbol rate
s Integrated adaptive equalizer (linear transversal equalizer or decision feedback
s DVB compatible differential decoding and mapping
s On chip DVB-C full compliant FEC decoder (de-interleaver, Reed-Solomon decoder
and de-scrambler)
s On chip MCNS full compliant FEC decoder (trellis demodulator, de-randomizer,
de-interleaver and Reed-Solomon decoder)
s Multiple TS JQAM filter
s Parallel and serial transport stream interface simultaneously
s I2C-bus interface, for easy control
3. Applications
s Cable set-top boxes
s Cable modems
s Cable Network Interface Modules (NIMs)
s Multichannel Multipoint Distribution Service (MMDS) (ETS 300-749) set-top boxes
9397 750 14559
Product data sheet
Rev. 01 — 12 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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भाग संख्याविवरणविनिर्माण
TDA10023HTSingle chip DVB-C/MCNS channel receiverPhilips

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