R8A66597BG डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - ASSP - Renesas Technology

भाग संख्या R8A66597BG
समारोह ASSP
मैन्युफैक्चरर्स Renesas Technology 
लोगो Renesas Technology लोगो 
पूर्व दर्शन
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R8A66597BG pdf
1.2.4 Compatible with all USB transfer types
Compatible with all USB transfer types, including isochronous transfer
Control transfer
Bulk transfer
Interrupt transfer (not compatible with high-bandwidth)
Isochronous transfer (not compatible with high-bandwidth)
1.2.5 Bus interface
16-bit CPU bus interface
Compatible with 16-bit separate bus/16-bit multiplex bus
Compatible with DMA transfer in 8-bit/16-bit access (slave function)
8-bit split bus (exclusive for external direct memory access controller (DMAC)) interface
Built-in two DMA interface channels DMA transfer provides 40MB/second high-performance data transfer
1.2.6 Pipe configuration
Built-in 8.5KB buffer memory for USB communication
Maximum of ten pipes can be selected (including default control pipe)
Programmable pipe configuration
Any endpoint address can be assigned to Pipe1 to Pipe9
Transfer conditions that can be written for each pipe
Pipe0: Control transfer, single buffer fixed at 256 bytes
Pipe1~Pipe2: Bulk transfer/Isochronous transfer, continuous transfer modes.
programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable)
Pipe3~Pipe5: Bulk transfer, continuous transfer modes,
programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable)
Pipe6~Pipe9: Interrupt transfer, single buffer fixed at 64 bytes
1.2.7 Features when selecting Host functions
Compatible with Hi-Speed (480Mbps), Full-Speed (12Mbps) and Low-Speed transfer (1.5Mbps)
Several Peripheral devices can be connected through one tier hub
Reset handshake auto response
SOF and packet transmission schedule automation
Transfer interval setup function for Isochronous and Interrupt transfer
1.2.8 Features when selecting Peripheral functions
Compatible with Hi-Speed (480Mbps) and Full-Speed transfer (12Mbps)
Auto identification of Hi-Speed or Full-Speed operations according to reset handshake auto response
Control transfer stage management function
Device state management function
Auto response function related to SET_ADDRESS request
NAK response interrupt function (NRDY)
SOF interpolation function
1.2.9 Functions that Provide On-The-Go Support
Built-in ID pin and ID pin monitor bit enables determination of A-Device/B-Device at start-up
Built-in control bit facilitates Host Negotiation Protocol
1.2.10 Other functions
Compatible with the CPU of big-endian or little-endian according to the byte-endian swap function
Transfer end function according to transaction count
End function of DMA transfer by external trigger (DEND pin)
SOF plus output function
Three types of input clock can be selected by built-in PLL
Select from 48MHz/24MHz/12MHz
Function to modify the BRDY interrupt event notification timing (BFRE)
Function to clear the auto buffer memory after the pipe data specified in the DxFIFO port is read (DCLRM)
Function to provide the auto clock from clock stop status
NAK setting function (SHTNAK) for PID response corresponding to transfer end
Rev1.01 Oct 17, 2008 Page 2 of 183

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R8A66597BGASSPRenesas Technology
Renesas Technology

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